SRAMWTSC

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Interpret as SRAMWTSC

ECCRAMRDWTEN=0, SRAM1WTEN=0, SRAM0WTEN=0

RAM Wait State Control Register

ECCRAMRDWTEN	ECCRAM Read wait enable 0 (0): Not add wait state in read access cycle to SRAM0 (ECC area) 1 (1): Add wait state in read access cycle to SRAM0 (ECC area)
SRAM0WTEN	SRAM0 Wait Enable 0 (0): Not add wait state in read access cycle to SRAM0 1 (1): Add wait state in read access cycle to SRAM0
SRAM1WTEN	SRAM1 Wait Enable 0 (0): Not add wait state in read access cycle to SRAM1 1 (1): Add wait state in read access cycle to SRAM1

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